The invention relates to an integrated circuit having at least two clock systems in which the appropriate clock signal, starting from a clock input, can be forwarded through clock trees to individual switching elements or switching blocks, and having at least one controlled switch which, for selected operating states, can be used to apply a single common clock signal to all clock trees, where at least a first clock tree has a PLL unit connected upstream of it, and an output of this clock tree is connected to an input of the PLL unit in order to form a phase locked loop.
Integrated circuits for digital applications contain xe2x80x9cclock treesxe2x80x9d. These are a tree-like structure for forwarding an input clock signal to the individual switching elements, normally flipflops, in the circuit.
The form of the clock trees depends on the number of flipflops in the subsystem, e.g. an.ASIC, and on the topology used. Depending on the number of stages it has and on its design, a clock tree in an ASIC can have, by way of example, 2000, 20 000, 40 000, etc. flipflops.
FIG. 1 shows the structure of an ASIC based on the prior art having two clock inputs TE1, TE2 for two clock trees CT1, CT2. The first clock signal CK1 is supplied from the clock input TE1 to the first clock tree CT1 via an input buffer EB1, a delay element DL1 and a PLL unit PL1. The clock signal is supplied to the appropriate register stages or flipflops possibly via further buffers in individual stages. For the clock tree CT1, a flipflop FF1x is shown at the end thereof by way of representation, and for the clock tree CT2 a flipflop FF2x is shown. A second clock signal CK2 is supplied from the clock input TE2 to the second clock tree CT2 via an input buffer EB2 and a controlled switch MU2, with the first clock signal CK1 also being routed to another input of the switch MU2.
For particular applications, in particular the xe2x80x9cBuilt In Self Testxe2x80x9d (=BIST), more than one clock system in an ASIC involves the clock systems being converted to a single clock system. However, this gives rise to the problem that the delay times from a clock input for the ASIC to the flipflop clock inputs for the subsidiary clock systems are different, since the clock trees have differences per se. The prior art solves this problem by using delay elements, reference being made in this case to the element DL1 in FIG. 1. Such delay elements adjust the path for the fastest clock treexe2x80x94in FIG. 1 the clock tree CT1xe2x80x94to the slowest path. A drawback of this solution is that the internal delay elements are firstly subject to a tolerance and to process variation and secondly need to be able to be turned off for a bypass when the short delay time of the clock tree in question is required in normal operation of the circuit.
It is an object of the invention to provide an integrated circuit in which, for particular operating states, a common clock signal can be applied to all clock trees such that the aforementioned problems with delay times etc. do not arise.
This object is achieved with an integrated circuit of the type mentioned in the introduction, in which, on the basis of the invention, each clock tree has an associated controlled switch, and the switches are actuated in the selected operating states such that the common clock signal is supplied only to a last clock tree, and an output of this clock tree is connected to the other input of the PLL unit for the at least first clock tree.
Since, for normal operation of an ASIC, a PLL unit is in many cases provided for delay time compensation for a clock tree, this unit is often present anyway, and one or more controlled switches (multiplexers) is/are required only for the first clock tree or for further clock trees. This provides an easy way of dynamically adjusting the delay time, and the process variation can be eliminated.
In one advantageous variant of the invention, a delay module whose delay corresponds to that of a controlled switch is connected between the output of the at least first clock tree and one input of the PLL unit. This allows the delay which has occurred in the controlled switches to be compensated for, if required, for the phase locked loop. The corresponding implementation is of particularly simple form if the delay module is an unactuated switch corresponding to the switchable switches.